1. Field of the Invention
The embodiments discussed herein are related to a semiconductor device.
2. Description of the Related Art
Improvement of the properties of 600V, 1200V, and 1700V rated power semiconductor devices such as insulated gate bipolar transistors (IGBT) and free wheeling diodes (FWD), hereinafter “diode”, is advancing. Such power semiconductor devices are used in power converting equipment such as highly efficient, power-saving inverters and are essential in motor control of power conversion equipment. Further, concerning power semiconductor devices for such power control applications, there is immediate market demand for properties of low loss (power-saving), high-speed, high efficiency, and environmental friendliness.
In response to such demands, for example, the following fabrication method has been proposed for IGBTs. First, with consideration of wafer crack prevention in the wafer process, the wafer process is started with a thick semiconductor wafer that is generally used. As far as possible, in the latter half of the wafer process, the semiconductor wafer is ground as thin as possible within an allowable range to obtain a given property, the semiconductor wafer is ground from a back side that is the opposite side of the semiconductor wafer with respect to the surface (front surface), which is the metal-oxide semiconductor gate (MOS gate) portion side of the semiconductor wafer. An activation process is performed of injecting an impurity by ion injection from the back surface after grinding of the semiconductor wafer, the impurity being of an impurity concentration sufficiently tested in terms of design, whereby a semiconductor device that has low electrical loss such as low turn-on voltage is completed at a low cost.
Recently, the development and structure of a low loss semiconductor device achieved at a low cost by the method of reducing the thickness of the semiconductor substrate (semiconductor wafer) as described above, has become mainstream particularly for power semiconductor devices. Further, consequent to introducing an impurity from the back surface after grinding of the semiconductor wafer as described above, for low loss IGBTs, a process step has to be performed of forming at a position on the substrate back surface side and deeper than a p+-type collector region, an n-type field stop (FS) layer of a higher impurity concentration than the n−-type drift layer. The n-type FS layer has a function of suppressing a depletion layer from reaching the p+-type collector region, the depletion layer extends from a pn junction between a n−-type drift layer and a p-type base region in an off state.
Further, to reduce the size of a related chip that includes an IGBT, development of a reverse conducting (RC) IGBT equipped with a vertical IGBT of a trench gate structure and a diode connected antiparallel to the vertical IGBT integrated on the same semiconductor substrate is advancing. A collector-shorted type device having only a trench structure portion (MOS gate portion) disposed on the substrate front surface side by a plane pattern similar to a typical IGBT, and having disposed in parallel on the substrate back surface side, an n+-type cathode region forming a diode portion and a p+-type collector region forming an IGBT portion has been proposed as an RC-IGBT (for example, refer to Japanese Patent Application Laid-Open Publication No. 2005-101514).
As another RC-IGBT, a device has been proposed that has a diode dedicated region in a diode portion (diode operating region) without disposing a trench structure portion of an n+-type emitter region, trench, gate insulating film, or gate electrode (for example, refer to Japanese Patent Application Laid-Open Publication No. 2008-192737). In the diode portion, for example, a p-intrinsic-n (PiN) diode, a Merged PiN Schottky (MPS) diode, etc. are disposed.
Further, a device in which a trench of the same shape as the IGBT portion is disposed in the diode portion has been proposed as another RC-IGBT (for example, refer to Japanese Patent Application Laid-Open Publication Nos. 2012-043890 and 2013-149909). Japanese Patent Application Laid-Open Publication Nos. 2012-043890 and 2013-149909 describe that in the diode portion, without disposal of an n+-type emitter region in p-type base region, and inside a trench through gate insulating film, a gate electrode of the emitter potential or the gate potential is embedded. Further, in Japanese Patent Application Laid-Open Publication No. 2013-149909, the trench pitch in the IGBT portion and in the diode portion differs.
As a structure that improves IGBT properties, a structure has been proposed for which the injection enhanced (IE) effect has been increased by making a portion of a gate insulating film formed along the trench inner wall and abutting the n−-type drift layer thicker than a portion abutting the p-type base region, whereby the width (distance between trenches (hereinafter, mesa width)) of the portion of the p-type base region between adjacent trenches (hereinafter, mesa portion) is reduced (for example, refer to Japanese Patent Application Laid-Open Publication No. 2010-251608). In Japanese Patent Application Laid-Open Publication No. 2010-251608, the trench width (width along the direction in which trenches are aligned) on the collector side is made wider than the emitter side, whereby the carrier concentration of the n−-type drift layer is increased and the ON voltage is lowered.
A conventional IGBT structure that reduces the width (mesa width) of the mesa portion between trenches as indicated in Japanese Patent Application Laid-Open Publication No. 2010-251608 will be described with reference to FIGS. 18A and 18B. FIGS. 18A and 18B are schematic views of a conventional IGBT gate structure. FIG. 18A depicts a planar structure of the substrate front surface side and FIG. 18B depicts a cross sectional structure along cutting plane line AA-AA′ of FIG. 18A. In FIGS. 18A and 18B, depiction of interlayer insulation films, emitter electrodes, and passivation films is omitted (similarly for FIGS. 19A and 19B). Further, in FIG. 18A, depiction of the gate insulating film is omitted (similarly for FIG. 19A). As depicted in FIGS. 18A and 18B, in a conventional IGBT, a p-type base region 102 is disposed in a superficial layer of a front surface of an n− type semiconductor substrate (semiconductor chip) forming an n−-type drift layer 101.
Trenches 103 are disposed from a front surface of the n−-type drift layer 101, through the p-type base region 102, reaching the n−-type drift layer 101. The trenches 103 are disposed in a striped-shape planar layout, separating the p-type base region 102 into plural regions (mesa portions). A gate electrode 105 is disposed inside the trench 103, via a gate insulating film 104. The width of the trench 103 is wider on the collector side than on the emitter side. The thickness of the gate insulating film 104 is thicker at a portion 104b of the collector side between the n−-type drift layer 101 and the gate electrode 105 than a portion 104a of the emitter side between an n+-type emitter region 106 described hereinafter and the gate electrode 105.
Inside the p-type base region 102, the n+-type emitter region 106 and a p+-type contact region 107 are selectively provided in each mesa portion. The n+-type emitter region 106 and the p+-type contact region 107 are disposed in a linear-shaped planar layout parallel to the trenches 103. An emitter electrode (not depicted) contacts the n+-type emitter region 106 and the p+-type contact region 107, and is electrically insulated from the gate electrode 105 by an interlayer insulation film (not depicted). In the superficial layer of the back surface of the n type semiconductor substrate, an n-type FS layer 109 is provided, and a p+-type collector region 111 is provided at a position that is shallower than the n-type FS layer 109. Reference numerals 108 and 110 respectively represent the emitter electrode and a collector region 110.
In such a conventional FS-IGBT, by simply combining a conventional diode, an RC-IGBT can be configured. FIGS. 19A and 19B are schematic views of a conventional RC-IGBT gate structure. FIG. 19A depicts a planar structure of the substrate front surface side and FIG. 19B depicts a cross sectional structure along cutting plane line BB-BB′ of FIG. 19A. As depicted in FIGS. 19A and 19B, on a single semiconductor substrate (semiconductor chip), an IGBT portion 121 forming an IGBT operating region and a diode portion 122 forming a diode operating region are provided. The structure of the IGBT in the IGBT portion 121 is similar to the FS-IGBT depicted in FIGS. 18A and 18B. In the diode portion 122, similar to the IGBT portion 121, the p-type base region 102, the trench 103, the gate insulating film 104, and the gate electrode 105 are provided in the substrate front surface side.
Further, in the diode portion 122, the p-type base region 102 functions as a p-type anode region and the n+-type emitter region 106 is not provided. The emitter electrode 108, in the diode portion 122, contacts the p-type base region 102 and functions as an anode electrode. The substrate back surface side is structured such that a portion of a p+-type collector region 111 is replaced by an n+-type cathode region 112. The p+-type collector region 111 opposes a MOS gate structure of the IGBT, across the n−-type drift layer 101. The n+-type cathode region 112 opposes a p-type anode region of the diode, across the n−-type drift layer 101. The collector region 110 contacts the p+-type collector region 111 and the n+-type cathode region 112, and functions as a cathode electrode. By configuring the diode portion 122 in this manner, the diode is connected antiparallel to the IGBT of the IGBT portion 121.
Nonetheless, in an RC-IGBT configured by simply combining a conventional IGBT and a conventional diode on a single semiconductor substrate as in Japanese Patent Application Laid-Open Publication Nos. 2005-101514, 2012-043890, and 2013-149909, when the mesa width is reduced and the IE effect of the IGBT is raised, diode properties deteriorate. More specifically, when the trench 103 having the width of the collector side wider than that of the emitter side is also disposed in the diode portion 122 and the mesa width is reduced as in Japanese Patent Application Laid-Open Publication No. 2010-251608 (refer to FIGS. 19A and 19B), although reduction of the size of the semiconductor chip is possible, the adverse effect of minority carrier removal being hindered becomes prominent during reverse recovery operation of the diode. Consequently, since minority carrier discharge takes time during reverse recovery operation of the diode, a problem arises in that reverse recovery current and reverse recovery loss become large. Such problems can be avoided by not providing the trench structure portion in the diode portion (diode operating region) and adopting a diode dedicated region as in Japanese Patent Application Laid-Open Publication No. 2008-192737. However, in this case, a problem arises in that at the bottom portion of trenches disposed near the border of the IGBT portion and the diode portion, electric field concentrates, and the breakdown voltage degrades.